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CAL
2005
13 years 5 months ago
On Reusing the Results of Pre-Executed Instructions in a Runahead Execution Processor
Previous research on runahead execution took it for granted as a prefetch-only technique. Even though the results of instructions independent of an L2 miss are correctly computed d...
Onur Mutlu, Hyesoon Kim, Jared Stark, Yale N. Patt
RTSS
2008
IEEE
13 years 11 months ago
Merging State and Preserving Timing Anomalies in Pipelines of High-End Processors
Many embedded systems are subject to temporal constraints that require advance guarantees on meeting deadlines. Such systems rely on static analysis to safely bound worst-case exe...
Sibin Mohan, Frank Mueller
RTAS
2008
IEEE
13 years 11 months ago
Hybrid Timing Analysis of Modern Processor Pipelines via Hardware/Software Interactions
Embedded systems are often subject to constraints that require determinism to ensure that task deadlines are met. Such systems are referred to as real-time systems. Schedulability...
Sibin Mohan, Frank Mueller
ICCAD
2001
IEEE
128views Hardware» more  ICCAD 2001»
14 years 2 months ago
An Assembly-Level Execution-Time Model for Pipelined Architectures
The aim of this work is to provide an elegant and accurate static execution timing model for 32-bit microprocessor instruction sets, covering also inter–instruction effects. Suc...
Giovanni Beltrame, Carlo Brandolese, William Forna...
HPCA
1998
IEEE
13 years 9 months ago
Supporting Highly-Speculative Execution via Adaptive Branch Trees
Most of the prediction mechanisms predict a single path to continue the execution on a branch. Alternatively, we may exploit parallelism from either possible paths of a branch, di...
Tien-Fu Chen