This paper describes a procedure for minimizing the power consumption in a boolean network under the zero delay model. Power is minimized by modifying the function of each interme...
Abstract. Parallel shared memory (PSM) routers represent an architectural approach for addressing the high memory bandwidth requirements dictated by output-queued switches. A funda...
This paper discusses the architecture and performance studies of Datacenter Optical Switch (DOS) designed for scalable and highthroughput interconnections within a data center. DO...
Xiaohui Ye, Yawei Yin, S. J. Ben Yoo, Paul Vincent...
On-chip interconnection networks (OCINs) have emerged as a modular and scalable solution for wire delay constraints in deep submicron VLSI design. OCIN research has shown that the ...
Avinash Karanth Kodi, Ashwini Sarathy, Ahmed Louri
The convergence of computers and the physical world is the theme for next generation networking research. This trend calls for real-time network infrastructure, which requires a h...
Qixin Wang, Sathish Gopalakrishnan, Xue Liu, Lui S...