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ICCAD
1994
IEEE
119views Hardware» more  ICCAD 1994»
13 years 8 months ago
Multi-level network optimization for low power
This paper describes a procedure for minimizing the power consumption in a boolean network under the zero delay model. Power is minimized by modifying the function of each interme...
Sasan Iman, Massoud Pedram
NETWORKING
2007
13 years 6 months ago
Accelerated Packet Placement Architecture for Parallel Shared Memory Routers
Abstract. Parallel shared memory (PSM) routers represent an architectural approach for addressing the high memory bandwidth requirements dictated by output-queued switches. A funda...
Brad Matthews, Itamar Elhanany, Vahid Tabatabaee
ANCS
2010
ACM
13 years 2 months ago
DOS: a scalable optical switch for datacenters
This paper discusses the architecture and performance studies of Datacenter Optical Switch (DOS) designed for scalable and highthroughput interconnections within a data center. DO...
Xiaohui Ye, Yawei Yin, S. J. Ben Yoo, Paul Vincent...
TC
2008
13 years 4 months ago
Adaptive Channel Buffers in On-Chip Interconnection Networks - A Power and Performance Analysis
On-chip interconnection networks (OCINs) have emerged as a modular and scalable solution for wire delay constraints in deep submicron VLSI design. OCIN research has shown that the ...
Avinash Karanth Kodi, Ashwini Sarathy, Ahmed Louri
RTAS
2008
IEEE
13 years 11 months ago
A Switch Design for Real-Time Industrial Networks
The convergence of computers and the physical world is the theme for next generation networking research. This trend calls for real-time network infrastructure, which requires a h...
Qixin Wang, Sathish Gopalakrishnan, Xue Liu, Lui S...