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HPCA
2005
IEEE
14 years 6 months ago
Using Virtual Load/Store Queues (VLSQs) to Reduce the Negative Effects of Reordered Memory Instructions
The use of large instruction windows coupled with aggressive out-oforder and prefetching capabilities has provided significant improvements in processor performance. In this paper...
Aamer Jaleel, Bruce L. Jacob
CC
2006
Springer
124views System Software» more  CC 2006»
13 years 9 months ago
Polyhedral Code Generation in the Real World
The polyhedral model is known to be a powerful framework to reason about high level loop transformations. Recent developments in optimizing compilers broke some generally accepted ...
Nicolas Vasilache, Cédric Bastoul, Albert C...
MICRO
2003
IEEE
125views Hardware» more  MICRO 2003»
13 years 11 months ago
WaveScalar
Silicon technology will continue to provide an exponential increase in the availability of raw transistors. Effectively translating this resource into application performance, how...
Steven Swanson, Ken Michelson, Andrew Schwerin, Ma...
ICPP
2002
IEEE
13 years 10 months ago
Software Caching using Dynamic Binary Rewriting for Embedded Devices
A software cache implements instruction and data caching entirely in software. Dynamic binary rewriting offers a means to specialize the software cache miss checks at cache miss t...
Chad Huneycutt, Joshua B. Fryman, Kenneth M. Macke...
BMCBI
2008
218views more  BMCBI 2008»
13 years 5 months ago
LOSITAN: A workbench to detect molecular adaptation based on a Fst-outlier method
Background: Testing for selection is becoming one of the most important steps in the analysis of multilocus population genetics data sets. Existing applications are difficult to u...
Tiago Antao, Ana Lopes, Ricardo J. Lopes, Albano B...