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EUROPAR
1999
Springer
13 years 8 months ago
Annotated Memory References: A Mechanism for Informed Cache Management
Processor cycle time continues to decrease faster than main memory access times, placing higher demands on cache memory hierarchy performance. To meet these demands, conventional ...
Alvin R. Lebeck, David R. Raymond, Chia-Lin Yang, ...
ISCA
1990
IEEE
186views Hardware» more  ISCA 1990»
13 years 8 months ago
Adaptive Software Cache Management for Distributed Shared Memory Architectures
An adaptive cache coherence mechanism exploits semantic information about the expected or observed access behavior of particular data objects. We contend that, in distributed shar...
John K. Bennett, John B. Carter, Willy Zwaenepoel
ISCA
1999
IEEE
187views Hardware» more  ISCA 1999»
13 years 8 months ago
Area Efficient Architectures for Information Integrity in Cache Memories
Information integrity in cache memories is a fundamental requirement for dependable computing. Conventional architectures for enhancing cache reliability using check codes make it...
Seongwoo Kim, Arun K. Somani
ICPP
2008
IEEE
13 years 11 months ago
Taming Single-Thread Program Performance on Many Distributed On-Chip L2 Caches
This paper presents a two-part study on managing distributed NUCA (Non-Uniform Cache Architecture) L2 caches in a future manycore processor to obtain high singlethread program per...
Lei Jin, Sangyeun Cho
WOSP
2004
ACM
13 years 10 months ago
Collecting whole-system reference traces of multiprogrammed and multithreaded workloads
The simulated evaluation of memory management policies relies on reference traces—logs of memory operations performed by running processes. No existing approach to reference tra...
Scott F. Kaplan