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SASP
2008
IEEE
183views Hardware» more  SASP 2008»
13 years 11 months ago
Application Acceleration with the Explicitly Parallel Operations System - the EPOS Processor
Different approaches have been proposed over the years for automatically transforming High-Level-Languages (HLL) descriptions of applications into custom hardware implementations. ...
Alexandros Papakonstantinou, Deming Chen, Wen-mei ...
IPPS
2010
IEEE
13 years 2 months ago
Speculative execution on multi-GPU systems
Abstract--The lag of parallel programming models and languages behind the advance of heterogeneous many-core processors has left a gap between the computational capability of moder...
Gregory F. Diamos, Sudhakar Yalamanchili
CASES
2009
ACM
13 years 11 months ago
CGRA express: accelerating execution using dynamic operation fusion
Coarse-grained reconfigurable architectures (CGRAs) present an appealing hardware platform by providing programmability with the potential for high computation throughput, scalab...
Yongjun Park, Hyunchul Park, Scott A. Mahlke
IPPS
2009
IEEE
13 years 11 months ago
Double Throughput Multiply-Accumulate unit for FlexCore processor enhancements
— As a simple five-stage General-Purpose Processor (GPP), the baseline FlexCore processor has a limited set of datapath units. By utilizing a flexible datapath interconnect and...
Tung Thanh Hoang, Magnus Själander, Per Larss...
ICPP
2009
IEEE
13 years 11 months ago
Speeding Up Distributed MapReduce Applications Using Hardware Accelerators
—In an attempt to increase the performance/cost ratio, large compute clusters are becoming heterogeneous at multiple levels: from asymmetric processors, to different system archi...
Yolanda Becerra, Vicenç Beltran, David Carr...