Instruction set customization accelerates the performance of applications by compressing the length of critical dependence paths and reducing the demands on processor resources. W...
Sami Yehia, Nathan Clark, Scott A. Mahlke, Kriszti...
Topology virtualization techniques are proposed for NoCbased many-core processors with core-level redundancy to isolate hardware changes caused by on-chip defective cores. Prior w...
Lei Zhang 0008, Yue Yu, Jianbo Dong, Yinhe Han, Sh...
This paper presents the first analysis of operating system execution on a simultaneous multithreaded (SMT) processor. While SMT has been studied extensively over the past 6 years,...
Abstract: Existing multicore systems already provide deep levels of thread parallelism. Hybrid programming models and composability of parallel libraries are very active areas of r...
Costin Iancu, Steven Hofmeyr, Filip Blagojevic, Yi...
In modern wireless devices, two broad classes of compute-intensive applications are common: those with high amounts of data-level parallelism, such as signal processing used in wi...
Ganesh S. Dasika, Mark Woh, Sangwon Seo, Nathan Cl...