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ISCA
2000
IEEE
105views Hardware» more  ISCA 2000»
13 years 9 months ago
Multiple-banked register file architectures
The register file access time is one of the critical delays in current superscalar processors. Its impact on processor performance is likely to increase in future processor genera...
José-Lorenzo Cruz, Antonio González,...
PODC
1994
ACM
13 years 9 months ago
Using Belief to Reason about Cache Coherence
The notion of belief has been useful in reasoning about authentication protocols. In this paper, we show how the notion of belief can be applied to reasoning about cache coherence...
Lily B. Mummert, Jeannette M. Wing, Mahadev Satyan...
USENIX
1993
13 years 6 months ago
HighLight: Using a Log-structured File System for Tertiary Storage Management
Robotic storage devices offer huge storage capacity at a low cost per byte, but with large access times. Integrating these devices into the storage hierarchy presents a challenge ...
John T. Kohl, Carl Staelin, Michael Stonebraker
USENIX
2008
13 years 7 months ago
Idle Read After Write - IRAW
Despite a low occurrence rate, silent data corruption represents a growing concern for storage systems designers. Throughout the storage hierarchy, from the file system down to th...
Alma Riska, Erik Riedel
ICS
2007
Tsinghua U.
13 years 11 months ago
An L2-miss-driven early register deallocation for SMT processors
The register file is one of the most critical datapath components limiting the number of threads that can be supported on a Simultaneous Multithreading (SMT) processor. To allow t...
Joseph J. Sharkey, Dmitry V. Ponomarev