Buffer caches in operating systems keep active file blocks in memory to reduce disk accesses. Related studies have been focused on how to minimize buffer misses and the caused pe...
The StrongARM processor features virtually-addressed caches and a TLB without address-space tags. A naive implementation therefore requires flushing of all CPU caches and the TLB ...
Adam Wiggins, Harvey Tuch, Volkmar Uhlig, Gernot H...
This paper describes PRISM, a distributed sharedmemory architecture that relies on a tightly integrated hardware and operating system design for scalable and reliable performance....
We present Opal, a light-weight framework for interactively locating missing web pages (http status code 404). Opal is an example of “in vivo” preservation: harnessing the col...
The frequency of accesses to remote data is a key factor affecting the performance of all Distributed Shared Memory (DSM) systems. Remote data caching is one of the most effective...