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» Approximate logic synthesis for error tolerant applications
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DAC
2003
ACM
14 years 7 months ago
Optimal integer delay budgeting on directed acyclic graphs
Delay budget is an excess delay each component of a design can tolerate under a given timing constraint. Delay budgeting has been widely exploited to improve the design quality. W...
Elaheh Bozorgzadeh, Soheil Ghiasi, Atsushi Takahas...
HPCA
2008
IEEE
14 years 6 months ago
Supporting highly-decoupled thread-level redundancy for parallel programs
The continued scaling of device dimensions and the operating voltage reduces the critical charge and thus natural noise tolerance level of transistors. As a result, circuits can p...
M. Wasiur Rashid, Michael C. Huang
IJACTAICIT
2010
200views more  IJACTAICIT 2010»
13 years 3 months ago
An Intelligent Framework for Natural Object Identification in Images
Human superiority over computers in identifying natural objects like clouds, water, grass etc. comes from two capabilities: the capability to maintain a growing knowledge base per...
Aasia Khanum
NCA
2006
IEEE
13 years 6 months ago
Evolutionary training of hardware realizable multilayer perceptrons
The use of multilayer perceptrons (MLP) with threshold functions (binary step function activations) greatly reduces the complexity of the hardware implementation of neural networks...
Vassilis P. Plagianakos, George D. Magoulas, Micha...
ICCAD
2005
IEEE
147views Hardware» more  ICCAD 2005»
14 years 2 months ago
NoCEE: energy macro-model extraction methodology for network on chip routers
In this paper we present NoCEE, a fast and accurate method for extracting energy models for packet-switched Network on Chip (NoC) routers. Linear regression is used to model the r...
Jeremy Chan, Sri Parameswaran