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CASES
2011
ACM
12 years 4 months ago
Architecting processors to allow voltage/reliability tradeoffs
Escalating variations in modern CMOS designs have become a threat to Moore’s law. While previous works have proposed techniques for tolerating variations by trading reliability ...
John Sartori, Rakesh Kumar
DSN
2005
IEEE
13 years 10 months ago
Engineering Over-Clocking: Reliability-Performance Trade-Offs for High-Performance Register Files
Register files are in the critical path of most high-performance processors and their latency is one of the most important factors that limit their size. Our goal is to develop er...
Gokhan Memik, Masud H. Chowdhury, Arindam Mallik, ...
DSN
2008
IEEE
13 years 10 months ago
Combined circuit and microarchitecture techniques for effective soft error robustness in SMT processors
As semiconductor technology scales, reliability is becoming an increasingly crucial challenge in microprocessor design. The rSRAM and voltage scaling are two promising circuit-lev...
Xin Fu, Tao Li, José A. B. Fortes
MICRO
2010
IEEE
153views Hardware» more  MICRO 2010»
13 years 2 months ago
AVF Stressmark: Towards an Automated Methodology for Bounding the Worst-Case Vulnerability to Soft Errors
Soft error reliability is increasingly becoming a first-order design concern for microprocessors, as a result of higher transistor counts, shrinking device geometries and lowering ...
Arun A. Nair, Lizy Kurian John, Lieven Eeckhout
ISLPED
2003
ACM
129views Hardware» more  ISLPED 2003»
13 years 9 months ago
A critical analysis of application-adaptive multiple clock processors
Enabled by the continuous advancement in fabrication technology, present day synchronous microprocessors include more than 100 million transistors and have clock speeds well in ex...
Emil Talpes, Diana Marculescu