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ISQED
2002
IEEE
83views Hardware» more  ISQED 2002»
13 years 11 months ago
A Hybrid BIST Architecture and Its Optimization for SoC Testing
This paper presents a hybrid BIST architecture and methods for optimizing it to test systems-on-chip in a cost effective way. The proposed self-test architecture can be implemente...
Gert Jervan, Zebo Peng, Raimund Ubar, Helena Kruus

Publication
209views
12 years 5 months ago
An Exploratory Study on Open Conversation Spaces in Global Software Engineering
Software engineering is by nature a highly collaborative activity and being able to collaborate effectively is a key factor for project success. However, collaborating effectivel...
Kevin Dullemond, Ben van Gameren, Rini van Solinge...
DSD
2010
IEEE
171views Hardware» more  DSD 2010»
13 years 4 months ago
Test Patterns Compression Technique Based on a Dedicated SAT-Based ATPG
— In this paper we propose a new method of test patterns compression based on a design of a dedicated SAT-based ATPG (Automatic Test Pattern Generator). This compression method i...
Jiri Balcarek, Petr Fiser, Jan Schmidt
AE
2007
Springer
14 years 15 days ago
Minimal and Necessary Conditions for the Emergence of Species-Specific Recognition Patterns
A simple mechanism is presented for the emergence of recognition patterns that are used by individuals to find each other and mate. The genetic component determines the brain of an...
Nicolas Brodu
ABIALS
2008
Springer
14 years 20 days ago
Anticipative Control of Voluntary Action: Towards a Computational Model
Abstract. Human action is goal-directed and must thus be guided by anticipations of wanted action effects. How anticipatory action control is possible and how it can emerge from ex...
Pascal Haazebroek, Bernhard Hommel