36 search results - page 2 / 8 » Architectural Power Optimization by Bus Splitting |
DAC
2004
ACM
14 years 6 months ago
2004
ACM
Power consumption, particularly runtime leakage, in long on-chip buses has grown to an unacceptable portion of the total power budget due to heavy buffer insertion to combat RC de...
JCP
2008
13 years 5 months ago
2008
A huge application domain, in particular, wireless and handheld devices strongly requires flexible and powerefficient hardware with high performance. This can only be achieved with...
CODES
1999
IEEE
13 years 9 months ago
1999
IEEE
The power consumption due to the HW/SW communication on system-level buses represents one of the major contributions to the overall power budget. A model to estimate the switching...
DAC
2001
ACM
14 years 6 months ago
2001
ACM
In modern embedded systems including communication and multimedia applications, large fraction of power is consumed during memory access and data transfer. Thus, buses should be d...
NOCS
2009
IEEE
14 years 1 days ago
2009
IEEE
While NoCs are efficient in delivering high throughput point-to-point traffic, their multi-hop operation is too slow for latency sensitive signals. In addition, NoCS are inefficie...