218 search results - page 1 / 44 » Architecture Level Power-Performance Tradeoffs for Pipelined... |
ISCAS
2007
IEEE
13 years 11 months ago
2007
IEEE
Abstract—This paper presents a method to investigate powerperformance tradeoffs in digital pipelined designs. The method is applied at the architectural level of the design. It w...
ICCAD
2001
IEEE
14 years 1 months ago
2001
IEEE
1 - This paper presents an efficient design exploration environment for high-end core processors. The heart of the proposed design exploration framework is a two-level simulation e...
TPDS
2008
13 years 5 months ago
2008
Multicore architectures have been ruling the recent microprocessor design trend. This is due to different reasons: better performance, thread-level parallelism bounds in modern app...
DATE
2005
IEEE
13 years 10 months ago
2005
IEEE
In this paper, we investigate the impact of Tox and Vth on power performance trade-offs for on-chip caches. We start by examining the optimization of the various components of a s...
DAC
2001
ACM
14 years 6 months ago
2001
ACM