Sciweavers

22 search results - page 1 / 5
» Architecture Support for Improving Bulk Memory Copying and I...
Sort
View
IEEEPACT
2009
IEEE
13 years 11 months ago
Architecture Support for Improving Bulk Memory Copying and Initialization Performance
—Bulk memory copying and initialization is one of the most ubiquitous operations performed in current computer systems by both user applications and Operating Systems. While many...
Xiaowei Jiang, Yan Solihin, Li Zhao, Ravishankar I...
CLUSTER
2007
IEEE
13 years 9 months ago
Efficient asynchronous memory copy operations on multi-core systems and I/OAT
Bulk memory copies incur large overheads such as CPU stalling (i.e., no overlap of computation with memory copy operation), small register-size data movement, cache pollution, etc...
Karthikeyan Vaidyanathan, Lei Chai, Wei Huang, Dha...
SPDP
1993
IEEE
13 years 9 months ago
Architectural Support for Block Transfers in a Shared-Memory Multiprocessor
This paper examines how the performance of a shared-memory multiprocessor can be improved by including hardware support for block transfers. A system similar to the Hector multipr...
Steven J. E. Wilton, Zvonko G. Vranesic
ISCA
1996
IEEE
130views Hardware» more  ISCA 1996»
13 years 9 months ago
Informing Memory Operations: Providing Memory Performance Feedback in Modern Processors
Memory latency is an important bottleneck in system performance that cannot be adequately solved by hardware alone. Several promising software techniques have been shown to addres...
Mark Horowitz, Margaret Martonosi, Todd C. Mowry, ...
CF
2010
ACM
13 years 10 months ago
On-chip communication and synchronization mechanisms with cache-integrated network interfaces
Per-core local (scratchpad) memories allow direct inter-core communication, with latency and energy advantages over coherent cache-based communication, especially as CMP architect...
Stamatis G. Kavadias, Manolis Katevenis, Michail Z...