130 search results - page 26 / 26 » Architecture and Evaluation of an Asynchronous Array of Simp... |
MICRO
2009
IEEE
13 years 11 months ago
2009
IEEE
Incorrect thread synchronization often leads to concurrency bugs that manifest nondeterministically and are difficult to detect and fix. Past work on detecting concurrency bugs ...
CGO
2010
IEEE
13 years 11 months ago
2010
IEEE
Tiling is a widely used loop transformation for exposing/exploiting parallelism and data locality. Effective use of tiling requires selection and tuning of the tile sizes. This is...
ISCA
2007
IEEE
13 years 10 months ago
2007
IEEE
Software cache-based side channel attacks are a serious new class of threats for computers. Unlike physical side channel attacks that mostly target embedded cryptographic devices,...
PPOPP
2005
ACM
13 years 10 months ago
2005
ACM
As the number of processors in today’s high performance computers continues to grow, the mean-time-to-failure of these computers are becoming significantly shorter than the exe...
NOCS
2007
IEEE
13 years 10 months ago
2007
IEEE
The paper introduces Network-on-Chip (NoC) design methodology and low cost mechanisms for supporting efficient cache access and cache coherency in future high-performance Chip Mul...