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ICPP
1991
IEEE
13 years 7 months ago
B-SYS: A 470-Processor Programmable Systolic Array
This paper presents an architecture for programmable systolic arrays that provides simple and e cient systolic communication. The Brown Systolic Array is a linear implementation o...
Richard Hughey, Daniel P. Lopresti
ISCA
2002
IEEE
105views Hardware» more  ISCA 2002»
13 years 9 months ago
Power and Performance Evaluation of Globally Asynchronous Locally Synchronous Processors
Due to shrinking technologies and increasing design sizes, it is becoming more difficult and expensive to distribute a global clock signal with low skew throughout a processor di...
Anoop Iyer, Diana Marculescu
RECONFIG
2008
IEEE
122views VLSI» more  RECONFIG 2008»
13 years 10 months ago
Using a CSP Based Programming Model for Reconfigurable Processor Arrays
The growing trend towards adoption of flexible and heterogeneous, parallel computing architectures has increased the challenges faced by the programming community. We propose a me...
Zain-ul-Abdin, Bertil Svensson
FPL
2007
Springer
120views Hardware» more  FPL 2007»
13 years 10 months ago
Design Methodology and Trade-offs Analysis for Parameterized Dynamically Reconfigurable Processor Arrays
In this paper, we propose a Dynamically Reconfigurable Processor Array (DRPA) generator which can generate various types of DRPAs. Our target DRPA architecture is fully parameter...
Yohei Hasegawa, Hideharu Amano
IPPS
2006
IEEE
13 years 10 months ago
Implementation of a programmable array processor architecture for approximate string matching algorithms on FPGAs
Approximate string matching problem is a common and often repeated task in information retrieval and bioinformatics. This paper proposes a generic design of a programmable array p...
Panagiotis D. Michailidis, Konstantinos G. Margari...