24 search results - page 5 / 5 » Architecture and compilation for data bandwidth improvement ... |
ICASSP
2008
IEEE
13 years 11 months ago
2008
IEEE
Multiple memory banks design is employed in many high performance DSP processors. This architectural feature supports higher memory bandwidth by allowing multiple data memory acce...
ASPLOS
2010
ACM
13 years 11 months ago
2010
ACM
SIMD (Single Instruction, Multiple Data) engines are an essential part of the processors in various computing markets, from servers to the embedded domain. Although SIMD-enabled a...
RTAS
2005
IEEE
13 years 10 months ago
2005
IEEE
While caches have become invaluable for higher-end architectures due to their ability to hide, in part, the gap between processor speed and memory access times, caches (and partic...
ICCAD
2008
IEEE
14 years 1 months ago
2008
IEEE
— As transistor sizes continue to shrink and the number of transistors per chip keeps increasing, chip multiprocessors (CMPs) are becoming a promising alternative to remain on th...