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ICIP
1999
IEEE
14 years 6 months ago
Architecture of Embedded Video Processing in a Multimedia Chip-Set
A new chip-set for video display processing in a consumer television or set-top box is presented. Key aspect of the chip-set is a high flexibility and programmability of multi-win...
Egbert G. T. Jaspers, Peter H. N. de With
CSREAESA
2006
13 years 6 months ago
A Dual-core Embedded System-on-Chip Architecture for Multimedia Signal Processing Applications
- This paper presents a dual-core embedded System-on-Chip for a wide range of application fields with particularly high processing demands, including general signal processing, vid...
Hong Yue, Kui Dai, Zhiying Wang
PATMOS
2000
Springer
13 years 8 months ago
Data-Reuse and Parallel Embedded Architectures for Low-Power, Real-Time Multimedia Applications
Exploitation of data re-use in combination with the use of custom memory hierarchy that exploits the temporal locality of data accesses may introduce significant power savings, esp...
Dimitrios Soudris, Nikolaos D. Zervas, Antonios Ar...
ICASSP
2009
IEEE
13 years 11 months ago
Bandwidth adaptive hardware architecture of K-Means clustering for intelligent video processing
K-Means is a clustering algorithm that is widely applied in many elds, including pattern classi cation and multimedia analysis. Due to real-time requirements and computational-cos...
Tse-Wei Chen, Shao-Yi Chien
ICIP
2000
IEEE
14 years 6 months ago
Performance Analysis of an H.263 Video Encoder for VIRAM
VIRAM (Vector Intelligent Random Access Memory) is a vector architecture processor with embedded memory, designed for portable multimedia processing devices. Its vector processing...
Thinh P. Q. Nguyen, Avideh Zakhor, Katherine A. Ye...