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DAC
2004
ACM
11 years 18 days ago
Architecture-level synthesis for automatic interconnect pipelining
For multi-gigahertz synchronous designs in nanometer technologies, multiple clock cycles are needed to cross the global interconnects, thus making it necessary to have pipelined g...
Jason Cong, Yiping Fan, Zhiru Zhang
MAM
2007
113views more  MAM 2007»
9 years 11 months ago
A reconfigurable computing framework for multi-scale cellular image processing
Cellular computing architectures represent an important class of computation that are characterized by simple processing elements, local interconnect and massive parallelism. Thes...
Reid B. Porter, Jan R. Frigo, Al Conti, Neal R. Ha...
CODES
2008
IEEE
10 years 6 months ago
Distributed flit-buffer flow control for networks-on-chip
The combination of flit-buffer flow control methods and latency-insensitive protocols is an effective solution for networks-on-chip (NoC). Since they both rely on backpressure...
Nicola Concer, Michele Petracca, Luca P. Carloni
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