3 search results - page 1 / 1 » Architecture-level synthesis for automatic interconnect pipe... |
DAC
2004
ACM
14 years 5 months ago
2004
ACM
For multi-gigahertz synchronous designs in nanometer technologies, multiple clock cycles are needed to cross the global interconnects, thus making it necessary to have pipelined g...
MAM
2007
13 years 4 months ago
2007
Cellular computing architectures represent an important class of computation that are characterized by simple processing elements, local interconnect and massive parallelism. Thes...
CODES
2008
IEEE
13 years 10 months ago
2008
IEEE
The combination of flit-buffer flow control methods and latency-insensitive protocols is an effective solution for networks-on-chip (NoC). Since they both rely on backpressure...