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TC
2010
12 years 11 months ago
Architectures and Execution Models for Hardware/Software Compilation and Their System-Level Realization
We propose an execution model that orchestrates the fine-grained interaction of a conventional general-purpose processor (GPP) and a high-speed reconfigurable hardware accelerator ...
Holger Lange, Andreas Koch
FPL
2007
Springer
105views Hardware» more  FPL 2007»
13 years 10 months ago
An Execution Model for Hardware/Software Compilation and its System-Level Realization
We introduce a new execution model for orchestrating the interaction between the conventional processor and the reconfigurable compute unit in adaptive computer systems. We then ...
Holger Lange, Andreas Koch
EUROMICRO
1998
IEEE
13 years 8 months ago
System Level Modelling for Hardware/Software Systems
Industry is facing a crisis in the design of complex hardware/software systems. Due to the increasing complexity, the gap between the generation of a product idea and the realisat...
Jeroen Voeten, P. H. A. van der Putten, Marc Geile...
MEMOCODE
2003
IEEE
13 years 9 months ago
MoDe: A Method for System-Level Architecture Evaluation
System-level design methodologies for embedded HW/SW systems face several challenges: In order to be susceptible to systematic formal analysis based on state-space exploration, a ...
Jan Romberg, Oscar Slotosch, Gabor Hahn
CC
2008
Springer
240views System Software» more  CC 2008»
13 years 6 months ago
Hardware JIT Compilation for Off-the-Shelf Dynamically Reconfigurable FPGAs
JIT compilation is a model of execution which translates at run time critical parts of the program to a low level representation. Typically a JIT compiler produces machine code fro...
Etienne Bergeron, Marc Feeley, Jean-Pierre David