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» Area delay estimation for digital signal processor cores
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CODES
2007
IEEE
13 years 12 months ago
A code-generator generator for multi-output instructions
We address the problem of instruction selection for Multi-Output Instructions (MOIs), producing more than one result. Such inherently parallel hardware instructions are very commo...
Hanno Scharwächter, Jonghee M. Youn, Rainer L...
ISCA
2010
IEEE
214views Hardware» more  ISCA 2010»
13 years 10 months ago
Re-architecting DRAM memory systems with monolithically integrated silicon photonics
The performance of future manycore processors will only scale with the number of integrated cores if there is a corresponding increase in memory bandwidth. Projected scaling of el...
Scott Beamer, Chen Sun, Yong-Jin Kwon, Ajay Joshi,...
SIGCOMM
2010
ACM
13 years 5 months ago
On the forwarding capability of mobile handhelds for video streaming over MANETs
Despite the importance of real-world experiments, nearly all ongoing research activities addressing video streaming over MANETs are based on simulation studies. Earlier research s...
Stein Kristiansen, Morten Lindeberg, Daniel Rodr&i...