Sciweavers

43 search results - page 9 / 9
» Area optimization of multi-cycle operators in high-level syn...
Sort
View
ICCD
1997
IEEE
158views Hardware» more  ICCD 1997»
13 years 9 months ago
Practical Advances in Asynchronous Design
Asynchronous systems are being viewed as an increasingly viable alternative to purely synchronous systems. This paper gives an overview of the current state of the art in practica...
Erik Brunvand, Steven M. Nowick, Kenneth Y. Yun
FPGA
2010
ACM
209views FPGA» more  FPGA 2010»
14 years 2 months ago
FPGA power reduction by guarded evaluation
Guarded evaluation is a power reduction technique that involves identifying sub-circuits (within a larger circuit) whose inputs can be held constant (guarded) at specific times d...
Chirag Ravishankar, Jason Helge Anderson
BMCBI
2010
150views more  BMCBI 2010»
13 years 5 months ago
AMS 3.0: prediction of post-translational modifications
Background: We present here the recent update of AMS algorithm for identification of post-translational modification (PTM) sites in proteins based only on sequence information, us...
Subhadip Basu, Dariusz Plewczynski