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    TVLSI
    2008
    121views more  TVLSI 2008»
    Area-Efficient Arithmetic Expression Evaluation Using Deeply Pipelined Floating-Point Cores
    13 years 4 months ago
    Area-Efficient Arithmetic Expression Evaluation Using Deeply Pipelined Floating-Point Cores
    Download  halcyon.usc.edu
    Recently, it has become possible to implement floating-point cores on field-programmable gate arrays (FPGAs) to provide acceleration for the myriad applications that require high-p...
    Ronald Scrofano, Ling Zhuo, Viktor K. Prasanna
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    FPGA
    2010
    ACM
    232views FPGA» more  FPGA 2010»
    High-throughput bayesian computing machine with reconfigurable hardware
    13 years 4 months ago
    High-throughput bayesian computing machine with reconfigurable hardware
    Download  isl.stanford.edu
    We use reconfigurable hardware to construct a high throughput Bayesian computing machine (BCM) capable of evaluating probabilistic networks with arbitrary DAG (directed acyclic gr...
    Mingjie Lin, Ilia Lebedev, John Wawrzynek
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