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» Arithmetic optimization for custom instruction set synthesis
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SASP
2009
IEEE
222views Hardware» more  SASP 2009»
13 years 11 months ago
Arithmetic optimization for custom instruction set synthesis
Abstract—One of the ways that custom instruction set extensions can improve over software execution is through the use of hardware structures that have been optimized at the arit...
Ajay K. Verma, Yi Zhu, Philip Brisk, Paolo Ienne
ASAP
2007
IEEE
123views Hardware» more  ASAP 2007»
13 years 6 months ago
Estimating Area Costs of Custom Instructions for FPGA-based Reconfigurable Processors
FPGA (Field Programmable Gate Array) based reconfigurable processor has been shown to meet the increasingly challenging performance targets and shorter time-to-market pressures. I...
Siew Kei Lam, Thambipillai Srikanthan
ICCAD
2009
IEEE
118views Hardware» more  ICCAD 2009»
13 years 2 months ago
Memory organization and data layout for instruction set extensions with architecturally visible storage
Present application specific embedded systems tend to choose instruction set extensions (ISEs) based on limitations imposed by the available data bandwidth to custom functional un...
Panagiotis Athanasopoulos, Philip Brisk, Yusuf Leb...
ASAP
2004
IEEE
160views Hardware» more  ASAP 2004»
13 years 8 months ago
Architectural Support for Arithmetic in Optimal Extension Fields
Public-key cryptosystems generally involve computation-intensive arithmetic operations, making them impractical for software implementation on constrained devices such as smart ca...
Johann Großschädl, Sandeep S. Kumar, Ch...
DATE
2006
IEEE
112views Hardware» more  DATE 2006»
13 years 10 months ago
Automating processor customisation: optimised memory access and resource sharing
We propose a novel methodology to generate Application Specific Instruction Processors (ASIPs) including custom instructions. Our implementation balances performance and area req...
Robert G. Dimond, Oskar Mencer, Wayne Luk