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TCBB
2010
144views more  TCBB 2010»
13 years 21 days ago
Querying Graphs in Protein-Protein Interactions Networks Using Feedback Vertex Set
Recent techniques increase rapidly the amount of our knowledge on interactions between proteins. The interpretation of these new information depends on our ability to retrieve kno...
Guillaume Blin, Florian Sikora, Stéphane Vi...
APSEC
2010
IEEE
12 years 9 months ago
Evaluating Cloud Platform Architecture with the CARE Framework
There is an emergence of cloud application platforms such as Microsoft’s Azure, Google’s App Engine and Amazon’s EC2/SimpleDB/S3. Startups and Enterprise alike, lured by the...
Liang Zhao, Anna Liu, Jacky Keung
CPP
2011
107views more  CPP 2011»
12 years 5 months ago
Simple, Functional, Sound and Complete Parsing for All Context-Free Grammars
Parsing text to identify grammatical structure is a common task, especially in relation to programming languages and associated tools such as compilers. Parsers for context-free g...
Tom Ridge
HIPEAC
2011
Springer
12 years 5 months ago
NoC-aware cache design for multithreaded execution on tiled chip multiprocessors
In chip multiprocessors (CMPs), data accesslatency dependson the memory hierarchy organization, the on-chip interconnect (NoC), and the running workload. Reducing data access late...
Ahmed Abousamra, Alex K. Jones, Rami G. Melhem
ISPD
2012
ACM
288views Hardware» more  ISPD 2012»
12 years 1 months ago
Construction of realistic gate sizing benchmarks with known optimal solutions
Gate sizing in VLSI design is a widely-used method for power or area recovery subject to timing constraints. Several previous works have proposed gate sizing heuristics for power ...
Andrew B. Kahng, Seokhyeong Kang