65 search results - page 13 / 13 » Automated Bus Generation for Multiprocessor SoC Design |
FCCM
2008
IEEE
13 years 11 months ago
2008
IEEE
Currently, only Xilinx Field Programmable Gate Arrays (FPGAs) support Dynamic Partial Reconfiguration (DPR). While there is currently some Computer Aided Design (CAD) tool support...
DAC
2006
ACM
14 years 6 months ago
2006
ACM
Three-dimensional (3-D) integrated circuits have emerged as promising candidates to overcome the interconnect bottlenecks of nanometer scale designs. While they offer several othe...
ISLPED
2005
ACM
13 years 11 months ago
2005
ACM
Network-on-chip (NoC) has been proposed as a solution for the global communication challenges of System-on-chip (SoC) design in the nanoscale technologies. NoC design with mesh ba...
CORR
2007
Springer
13 years 5 months ago
2007
Springer
This paper deals with a common verification methodology and environment for SystemC BCA and RTL models. The aim is to save effort by avoiding the same work done twice by different...
DAC
2002
ACM
14 years 6 months ago
2002
ACM
The next generation of computer chips will continue the trend for more complexity than their predecessors. Many of them will contain different chip technologies and are termed SoC...