119 search results - page 1 / 24 » Automated Modeling of Custom Digital Circuits for Test |
DATE
2002
IEEE
13 years 10 months ago
2002
IEEE
Models meant for logic verification and simulation are often used for ATPG. For custom digital circuits, these models contain many tristate devices, which leads to lower fault co...
APIN
2002
13 years 4 months ago
2002
This paper describes a new learning by example mechanism and its application for digital circuit design automation. This mechanism uses finite state machines to represent the infer...
PATMOS
2005
Springer
13 years 10 months ago
2005
Springer
This paper presents a modular optimization framework for custom digital circuits in the power – performance space. The method uses a static timer and a nonlinear optimizer to max...
ICCAD
2001
IEEE
14 years 1 months ago
2001
IEEE
: This paper describes ASF, a novel cell-level analog synthesis framework that can size and bias a given circuit topology subject to a set of performance objectives and a manufactu...
MTDT
2003
IEEE
13 years 10 months ago
2003
IEEE
ct Defect-based testing for digital logic concentrates primarily on methods of test application, including for example at-speed structural tests and IDDQ testing. In contrast, defe...