4359 search results - page 1 / 872 » Automated Pipeline Design |
TVCG
2008
13 years 4 months ago
2008
Building visualization and analysis pipelines is a large hurdle in the adoption of visualization and workflow systems by domain scientists. In this paper, we propose techniques to ...
DAC
2001
ACM
14 years 5 months ago
2001
ACM
DAC
2001
ACM
14 years 5 months ago
2001
ACM
The interlock and forwarding logic is considered the tricky part of a fully-featured pipelined microprocessor and especially debugging these parts delays the hardware design proce...
ACSD
2005
IEEE
13 years 10 months ago
2005
IEEE
Register Transfer Level (RTL) synthesis model which simplified the design of clocked circuits allowed design automation boost and VLSI progress for more than a decade. Shrinking t...
JAR
2006
13 years 4 months ago
2006
We describe an approach to verifying bit-level pipelined machine models using a combination of deductive reasoning and decision procedures. While theorem proving systems such as AC...