557 search results - page 1 / 112 » Automatic Abstraction for Verification of Timed Circuits and... |
CAV
2001
Springer
13 years 10 months ago
2001
Springer
ICCD
1999
IEEE
13 years 9 months ago
1999
IEEE
ions", in IEEE Transactions on CAD of VLSI, 25(3):403-412, March, 2006. , E. Mercer, C. Myers, "Modular Verification of Timed Systems Using Automatic Abstraction" in...
CAV
1994
Springer
13 years 9 months ago
1994
Springer
This paper presents a new formalism and a new algorithm for verifying timed circuits. The formalism, called orbital nets, allows hierarchical verification based on abehavioralseman...
ASPDAC
2004
ACM
13 years 9 months ago
2004
ACM
When time is incorporated in the specification of discrete systems, the complexity of verification grows exponentially. When the temporal behavior is specified with symbols, the ve...
ICCAD
2002
IEEE
14 years 2 months ago
2002
IEEE
In this paper we present an advanced functional extraction tool for automatic generation of high-level RTL from switch-level circuit netlist representation. The tool is called FEV...