101 search results - page 1 / 21 » Automatic Clock Abstraction from Sequential Circuits |
DAC
1995
ACM
13 years 8 months ago
1995
ACM
Our goal is to transform a low-level circuit design into a more representation. A pre-existing tool, Tranalyze [4], takes a switch-level circuit and generates a functionally equiv...
ASPDAC
2000
ACM
13 years 9 months ago
2000
ACM
– This paper presents a novel circuit design technique to reduce the power dissipation in sequential circuits by generating a quasi-synchronous derived clock from the master cloc...
ICCD
1997
IEEE
13 years 8 months ago
1997
IEEE
Abstract— In this paper we consider the problem of clustering sequential circuits subject to a bound on the area of each cluster, with the objective of minimizing the clock perio...
DATE
2004
IEEE
13 years 8 months ago
2004
IEEE
This paper presents a methodology to derive asynchronous circuits from optimized synchronous circuits by replacing the clock distribution tree by a handshaking network. A case stu...
DAC
2000
ACM
14 years 5 months ago
2000
ACM
In this paper we describe an area efficient power minimization scheme "Control Generated ClockingI` that saves significant amounts of power in datapath registers and clock dr...