41 search results - page 3 / 9 » Automatic Generation of Synchronous Test Patterns for Asynch... |
EURODAC
1990
IEEE
13 years 10 months ago
1990
IEEE
In this paper an efficient cone oriented circuit partitioning method is presented, which significantly speeds up automatic test pattern generation for combinational circuits. The ...
DSD
2005
IEEE
13 years 11 months ago
2005
IEEE
Current paper presents new alternatives for accelerating the task of fault simulation for sequential circuits by hardware emulation on FPGA. Fault simulation is an important subta...
VLSID
2009
IEEE
14 years 6 months ago
2009
IEEE
We present the automatic test pattern generator TIGUAN based on a thread-parallel SAT solver. Due to a tight integration of the SAT engine into the ATPG algorithm and a carefully ...
DSD
2010
IEEE
13 years 4 months ago
2010
IEEE
— In this paper we propose a new method of test patterns compression based on a design of a dedicated SAT-based ATPG (Automatic Test Pattern Generator). This compression method i...
ATS
2000
IEEE
13 years 10 months ago
2000
IEEE
At very high frequencies, the major potential of asynchronous circuits is absence of clock skew and, through that, better exploitation of relative timing relations. This paper pre...