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LCTRTS
2005
Springer
13 years 10 months ago
Cache aware optimization of stream programs
Effective use of the memory hierarchy is critical for achieving high performance on embedded systems. We focus on the class of streaming applications, which is increasingly preval...
Janis Sermulins, William Thies, Rodric M. Rabbah, ...
PPOPP
2006
ACM
13 years 11 months ago
Performance characterization of molecular dynamics techniques for biomolecular simulations
Large-scale simulations and computational modeling using molecular dynamics (MD) continues to make significant impacts in the field of biology. It is well known that simulations...
Sadaf R. Alam, Jeffrey S. Vetter, Pratul K. Agarwa...
ICS
2001
Tsinghua U.
13 years 9 months ago
Multiplex: unifying conventional and speculative thread-level parallelism on a chip multiprocessor
Recent proposals for Chip Multiprocessors (CMPs) advocate speculative, or implicit, threading in which the hardware employs prediction to peel off instruction sequences (i.e., imp...
Chong-liang Ooi, Seon Wook Kim, Il Park, Rudolf Ei...
SIGMETRICS
2011
ACM
178views Hardware» more  SIGMETRICS 2011»
12 years 8 months ago
Soft error benchmarking of L2 caches with PARMA
The amount of charge stored in an SRAM cell shrinks rapidly with each technology generation thus increasingly exposing caches to soft errors. Benchmarking the FIT rate of caches d...
Jinho Suh, Mehrtash Manoochehri, Murali Annavaram,...
CASES
2005
ACM
13 years 7 months ago
Optimizing stream programs using linear state space analysis
Digital Signal Processing (DSP) is becoming increasingly widespread in portable devices. Due to harsh constraints on power, latency, and throughput in embedded environments, devel...
Sitij Agrawal, William Thies, Saman P. Amarasinghe