Sciweavers

23 search results - page 4 / 5
» Automatic measurement of memory hierarchy parameters
Sort
View
ASPLOS
2006
ACM
13 years 11 months ago
Software-based instruction caching for embedded processors
While hardware instruction caches are present in virtually all general-purpose and high-performance microprocessors today, many embedded processors use SRAM or scratchpad memories...
Jason E. Miller, Anant Agarwal
PARA
2004
Springer
13 years 10 months ago
A Family of High-Performance Matrix Multiplication Algorithms
During the last half-decade, a number of research efforts have centered around developing software for generating automatically tuned matrix multiplication kernels. These include ...
John A. Gunnels, Fred G. Gustavson, Greg Henry, Ro...
DATE
2008
IEEE
168views Hardware» more  DATE 2008»
13 years 11 months ago
Cycle-approximate Retargetable Performance Estimation at the Transaction Level
This paper presents a novel cycle-approximate performance estimation technique for automatically generated transaction level models (TLMs) for heterogeneous multicore designs. The...
Yonghyun Hwang, Samar Abdi, Daniel Gajski
TKDE
2010
224views more  TKDE 2010»
13 years 3 months ago
Probabilistic Topic Models for Learning Terminological Ontologies
—Probabilistic topic models were originally developed and utilised for document modeling and topic extraction in Information Retrieval. In this paper we describe a new approach f...
Wang Wei, Payam M. Barnaghi, Andrzej Bargiela
HPCA
2006
IEEE
14 years 5 months ago
Phase characterization for power: evaluating control-flow-based and event-counter-based techniques
Computer systems increasingly rely on dynamic, phasebased system management techniques, in which system hardware and software parameters may be altered or tuned at runtime for dif...
Canturk Isci, Margaret Martonosi