65 search results - page 3 / 13 » Automatic parallel code generation for tiled nested loops |
ICS
1999
Tsinghua U.
13 years 10 months ago
1999
Tsinghua U.
On modern computers, the performance of programs is often limited by memory latency rather than by processor cycle time. To reduce the impact of memory latency, the restructuring ...
EUROPAR
1999
Springer
13 years 10 months ago
1999
Springer
This paper describes a tiling technique that can be used by application programmers and optimizing compilers to obtain I/O-efficient versions of regular scientific loop nests. Du...
IEEEPACT
2009
IEEE
14 years 23 days ago
2009
IEEE
—Analytical models have been used to estimate optimal values for parameters such as tile sizes in the context of loop nests. However, important algorithms such as fast Fourier tr...
TPDS
2002
13 years 5 months ago
2002
In this paper, an efficient algorithm to implement loop partitioning is introduced and evaluated. We start from results of Agarwal et al. [1] whose aim is to minimize the number of...
SC
1991
ACM
13 years 9 months ago
1991
ACM
We present a new approach that enables compiler optimization of procedure calls and loop nests containing procedure calls. We introduce two interprocedural transformationsthat mov...