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DATE
1999
IEEE
147views Hardware» more  DATE 1999»
13 years 9 months ago
Efficient BIST Hardware Insertion with Low Test Application Time for Synthesized Data Paths
In this paper, new and efficient BIST methodology and BIST hardware insertion algorithms are presented for RTL data paths obtained from high level synthesis. The methodology is ba...
Nicola Nicolici, Bashir M. Al-Hashimi
TAP
2008
Springer
93views Hardware» more  TAP 2008»
13 years 5 months ago
Pex-White Box Test Generation for .NET
Pex automatically produces a small test suite with high code coverage for a .NET program. To this end, Pex performs a systematic program analysis (using dynamic symbolic execution,...
Nikolai Tillmann, Jonathan de Halleux
IFIP
2010
Springer
12 years 12 months ago
Model Checking of Concurrent Algorithms: From Java to C
Concurrent software is difficult to verify. Because the thread schedule is not controlled by the application, testing may miss defects that occur under specific thread schedules. T...
Cyrille Artho, Masami Hagiya, Watcharin Leungwatta...
PASTE
2010
ACM
13 years 10 months ago
Opportunities for concurrent dynamic analysis with explicit inter-core communication
Multicore is now the dominant processor trend, and the number of cores is rapidly increasing. The paradigm shift to multicore forces the redesign of the software stack, which incl...
Jungwoo Ha, Stephen P. Crago
SEKE
2005
Springer
13 years 10 months ago
Application of Design Combinatorial Theory to Scenario-Based Software Architecture Analysis
Design combinatorial theory for test-case generation has been used successfully in the past. It is useful in optimizing test cases as it is practically impossible to exhaustively t...
Chung-Horng Lung, Marzia Zaman