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» Balance Testing of Logic Circuits
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PLDI
2010
ACM
13 years 10 months ago
Mixing type checking and symbolic execution
Static analysis designers must carefully balance precision and efficiency. In our experience, many static analysis tools are built around an elegant, core algorithm, but that alg...
Yit Phang Khoo, Bor-Yuh Evan Chang, Jeffrey S. Fos...
JSAC
2010
214views more  JSAC 2010»
13 years 3 months ago
IEEE 802.15.5 WPAN mesh standard-low rate part: Meshing the wireless sensor networks
—This paper introduces a new IEEE standard, IEEE 802.15.5,which provides mesh capability for wireless personal area network (WPAN) devices. The standard provides an architectural...
Myung J. Lee, Rui Zhang, Jianliang Zheng, Gahng-Se...
MTDT
2003
IEEE
100views Hardware» more  MTDT 2003»
13 years 10 months ago
Optimal Spare Utilization in Repairable and Reliable Memory Cores
Advances in System-on-Chip (SoC) technology rely on manufacturing and assembling high-performance system cores for many critical applications. Among these cores, memory occupies t...
Minsu Choi, Nohpill Park, Fabrizio Lombardi, Yong-...