28 search results - page 2 / 6 » Balancing memory and performance through selective flushing ... |
PARA
2004
Springer
13 years 10 months ago
2004
Springer
Cache optimizations typically include code transformations to increase the locality of memory accesses. An orthogonal approach is to enable for latency hiding by introducing prefet...
CGO
2005
IEEE
13 years 10 months ago
2005
IEEE
Modern embedded microprocessors use low power on-chip memories called scratch-pad memories to store frequently executed instructions and data. Unlike traditional caches, scratch-p...
EMSOFT
2010
Springer
13 years 2 months ago
2010
Springer
We propose the first polynomial-time code selection algorithm for minimising the worst-case execution time of a nonnested loop executed on a fully pipelined processor that uses sc...
CASES
2010
ACM
13 years 2 months ago
2010
ACM
The performance of most embedded systems is critically dependent on the memory hierarchy performance. In particular, higher cache hit rate can provide significant performance boos...
ECRTS
2006
IEEE
13 years 10 months ago
2006
IEEE
Cache memories have been extensively used to bridge the gap between high speed processors and relatively slower main memories. However, they are sources of predictability problems...