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MEMOCODE
2003
IEEE
13 years 10 months ago
LOTOS Code Generation for Model Checking of STBus Based SoC: the STBus interconnect
In the design process of SoC (System on Chip), validation is one of the most critical and costly activity. The main problem for industrial companies like STMicroelectronics, stand...
Pierre Wodey, Geoffrey Camarroque, Fabrice Baray, ...
ENTCS
2008
146views more  ENTCS 2008»
13 years 5 months ago
Probabilistic Abstract Interpretation of Imperative Programs using Truncated Normal Distributions
istic Abstract Interpretation of Imperative Programs using Truncated Normal Distributions Michael J. A. Smith1 ,2 Laboratory for Foundations of Computer Science University of Edinb...
Michael J. A. Smith
JLP
2006
108views more  JLP 2006»
13 years 4 months ago
On testing UML statecharts
We present a formal framework for notions related to testing and model based test generation for a behavioural subset of UML Statecharts (UMLSCs). This framework builds, on one ha...
Mieke Massink, Diego Latella, Stefania Gnesi