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TC
2011
13 years 7 days ago
Software-Based Cache Coherence with Hardware-Assisted Selective Self-Invalidations Using Bloom Filters
— Implementing shared memory consistency models on top of hardware caches gives rise to the well-known cache coherence problem. The standard solution involves implementing cohere...
Thomas J. Ashby, Pedro Diaz, Marcelo Cintra
MASCOTS
2004
13 years 7 months ago
Architecture Independent Performance Characterization and Benchmarking for Scientific Applications
A simple, tunable, synthetic benchmark with a performance directly related to applications would be of great benefit to the scientific computing community. In this paper, we prese...
Erich Strohmaier, Hongzhang Shan
SIGMETRICS
2011
ACM
178views Hardware» more  SIGMETRICS 2011»
12 years 8 months ago
Soft error benchmarking of L2 caches with PARMA
The amount of charge stored in an SRAM cell shrinks rapidly with each technology generation thus increasingly exposing caches to soft errors. Benchmarking the FIT rate of caches d...
Jinho Suh, Mehrtash Manoochehri, Murali Annavaram,...
ESCIENCE
2006
IEEE
13 years 12 months ago
Characterization of Computational Grid Resources Using Low-Level Benchmarks
An important factor that needs to be taken into account by end-users and systems (schedulers, resource brokers, policy brokers) when mapping applications to the Grid, is the perfo...
George Tsouloupas, Marios D. Dikaiakos
PPOPP
2009
ACM
14 years 6 months ago
Transactional memory with strong atomicity using off-the-shelf memory protection hardware
This paper introduces a new way to provide strong atomicity in an implementation of transactional memory. Strong atomicity lets us offer clear semantics to programs, even if they ...
Martín Abadi, Tim Harris, Mojtaba Mehrara