2 search results - page 1 / 1 » Block alignment in 3D floorplan using layered TCG |
GLVLSI
2006
IEEE
13 years 10 months ago
2006
IEEE
In modern IC design, the number of long on-chip wires has been growing rapidly because of the increasing circuit complexity. Interconnect delay has dominated over gate delay as te...
ICCD
2007
IEEE
14 years 1 months ago
2007
IEEE
Most previous 3D IC research focused on “stacking” traditional 2D silicon layers, so the interconnect reduction is limited to interblock delays. In this paper, we propose tech...