3 search results - page 1 / 1 » BlockChop: Dynamic squash elimination for hybrid processor a... |
ISCA
2012
IEEE
11 years 7 months ago
2012
IEEE
Hybrid processors are HW/SW co-designed processors that leverage blocked-execution, the execution of regions of instructions as atomic blocks, to facilitate aggressive speculative...
IEEEPACT
2007
IEEE
13 years 11 months ago
2007
IEEE
In this paper we propose a unified architectural support that can be used flexibly for either soft-error protection or software bug detection. Our approach is based on dynamically...
HPCA
2002
IEEE
14 years 4 months ago
2002
IEEE
Cache memories account for a significant fraction of a chip's overall energy dissipation. Recent research advocates using "resizable" caches to exploit cache requir...