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» Branch Optimisation Techniques for Hardware Compilation
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FPL
2003
Springer
259views Hardware» more  FPL 2003»
9 years 10 months ago
Branch Optimisation Techniques for Hardware Compilation
Abstract. This paper explores using information about program branch probabilities to optimise reconīŦgurable designs. The basic premise is to promote utilization by dedicating mo...
Henry Styles, Wayne Luk
MICRO
1996
IEEE
142views Hardware» more  MICRO 1996»
9 years 9 months ago
Compiler Synthesized Dynamic Branch Prediction
Branch prediction is the predominant approach for minimizing the pipeline breaks caused by branch instructions. Traditionally, branch prediction is accomplished in one of two ways...
Scott A. Mahlke, Balas K. Natarajan
MICRO
1994
IEEE
118views Hardware» more  MICRO 1994»
9 years 9 months ago
Characterizing the impact of predicated execution on branch prediction
Branch instructions are recognized as a major impediment to exploiting instruction level parallelism. Even with sophisticated branch prediction techniques, many frequently execute...
Scott A. Mahlke, Richard E. Hank, Roger A. Bringma...
ISSS
1995
IEEE
104views Hardware» more  ISSS 1995»
9 years 9 months ago
A path-based technique for estimating hardware runtime in HW/SW-cosynthesis
One of the key issues in hardware/software{cosynthesis is precise estimation. The usual local estimation techniques are inadequate for globally optimising compilers and synthesis ...
Jörg Henkel, Rolf Ernst
HPCA
1997
IEEE
9 years 9 months ago
Architectural Support for Compiler-Synthesized Dynamic Branch Prediction Strategies: Rationale and Initial Results
This paper introduces a new architectural approach that supports compiler-synthesized dynamic branch predication. In compiler-synthesized dynamic branch prediction, the compiler g...
David I. August, Daniel A. Connors, John C. Gyllen...
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