30 search results - page 1 / 6 » Branch-mispredict level parallelism (BLP) for control indepe... |
HPCA
2008
IEEE
14 years 6 months ago
2008
IEEE
A microprocessor's performance is fundamentally limited by the rate at which it can resolve branch mispredictions. Control independence (CI) architectures look for useful con...
HPCA
2004
IEEE
14 years 6 months ago
2004
IEEE
Branch misprediction penalty consists of two components: the time wasted on mis-speculative execution until the mispredicted branch is resolved and the time to restart the pipelin...
IPPS
2005
IEEE
13 years 11 months ago
2005
IEEE
Current processors exploit out-of-order execution and branch prediction to improve instruction level parallelism. When a branch prediction is wrong, processors flush the pipeline ...
MICRO
1999
IEEE
13 years 10 months ago
1999
IEEE
Branch mispredictions are a major obstacle to exploiting instruction-level parallelism, at least in part because all instructions after a mispredicted branch are squashed. However...
ISCA
2000
IEEE
13 years 10 months ago
2000
IEEE
For many applications, branch mispredictions and cache misses limit a processor’s performance to a level well below its peak instruction throughput. A small fraction of static i...