6 search results - page 1 / 2 » Buffered Routing Tree Construction under Buffer Placement Bl... |
VLSID
2002
IEEE
14 years 4 months ago
2002
IEEE
Interconnect delay has become a critical factor in determining the performance of integrated circuits. Routing and buffering are powerful means of improving the circuit speed and ...
DAC
2005
ACM
14 years 5 months ago
2005
ACM
This paper presents the first in-depth study on applying dual Vdd buffers to buffer insertion and multi-sink buffered tree construction for power minimization under delay constrai...
VLSID
2005
IEEE
14 years 4 months ago
2005
IEEE
Buffer insertion method plays a great role in modern VLSI design. Many buffer insertion algorithms have been proposed in recent years. However, most of them used simplified delay ...
ASPDAC
2012
ACM
12 years 6 days ago
2012
ACM
— In this paper, we present an obstacle-aware clock tree synthesis method for through-silicon-via (TSV)-based 3D ICs. A unique aspect of this problem lies in the fact that variou...
DATE
2002
IEEE
13 years 9 months ago
2002
IEEE
In this paper, we address the problem of simultaneous routing and buffer insertion. Recently in [12, 22], the authors considered simultaneous maze routing and buffer insertion und...