40 search results - page 1 / 8 » Buffering Interconnect for Multicore Processor Designs |
TCAD
2008
13 years 4 months ago
2008
Recently, the microprocessor industry is headed in the direction of multicore designs in order to continue the chip performance growth. We investigate buffer insertion, which is a ...
ISPASS
2007
IEEE
13 years 10 months ago
2007
IEEE
We have studied DRAM-level prefetching for the fully buffered DIMM (FB-DIMM) designed for multi-core processors. FB-DIMM has a unique two-level interconnect structure, with FB-DIM...
DATE
2009
IEEE
13 years 11 months ago
2009
IEEE
Abstract— In many current SoCs, the architectural interface to onchip monitors is ad hoc and inefficient. In this paper, a new architectural approach which advocates the use of a...
EUROSYS
2011
ACM
12 years 8 months ago
2011
ACM
Buffer caches in operating systems keep active file blocks in memory to reduce disk accesses. Related studies have been focused on how to minimize buffer misses and the caused pe...
JEC
2006
13 years 4 months ago
2006
We present an overview of the Synchroscalar single-chip, multi-core processor. Through the design of Synchroscalar, we find that high energy efficiency and low complexity can be a...