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» Buffering Interconnect for Multicore Processor Designs
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ISCA
1999
IEEE
88views Hardware» more  ISCA 1999»
13 years 9 months ago
A Scalable Front-End Architecture for Fast Instruction Delivery
In the pursuit of instruction-level parallelism, significant demands are placed on a processor's instruction delivery mechanism. Delivering the performance necessary to meet ...
Glenn Reinman, Todd M. Austin, Brad Calder
PVM
2009
Springer
13 years 11 months ago
Hierarchical Collectives in MPICH2
Abstract. Most parallel systems on which MPI is used are now hierarchical: some processors are much closer to others in terms of interconnect performance. One of the most common su...
Hao Zhu, David Goodell, William Gropp, Rajeev Thak...
BMCBI
2008
89views more  BMCBI 2008»
13 years 5 months ago
R/parallel - speeding up bioinformatics analysis with R
Background: R is the preferred tool for statistical analysis of many bioinformaticians due in part to the increasing number of freely available analytical methods. Such methods ca...
Gonzalo Vera, Ritsert C. Jansen, Remo Suppi
CLUSTER
2002
IEEE
13 years 9 months ago
Scalable Resource Management in High Performance Computers
Clusters of workstations have emerged as an important platform for building cost-effective, scalable, and highlyavailable computers. Although many hardware solutions are available...
Eitan Frachtenberg, Fabrizio Petrini, Juan Fern&aa...
RSP
2000
IEEE
156views Control Systems» more  RSP 2000»
13 years 9 months ago
Quasi-Static Scheduling of Reconfigurable Dataflow Graphs for DSP Systems
Dataflow programming has proven to be popular for representing applications in rapid prototyping tools for digital signal processing (DSP); however, existing dataflow design tools...
Bishnupriya Bhattacharya, Shuvra S. Bhattacharyya