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» BulkSMT: Designing SMT processors for atomic-block execution
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HPCA
2005
IEEE
13 years 11 months ago
Chip Multithreading: Opportunities and Challenges
Chip Multi-Threaded (CMT) processors provide support for many simultaneous hardware threads of execution in various ways, including Simultaneous Multithreading (SMT) and Chip Mult...
Lawrence Spracklen, Santosh G. Abraham
ISCAPDCS
2004
13 years 6 months ago
An Adaptive OpenMP Loop Scheduler for Hyperthreaded SMPs
Hyperthreaded(HT) and simultaneous multithreaded (SMT) processors are now available in commodity workstations and servers. This technology is designed to increase throughput by ex...
Yun Zhang, Mihai Burcea, Victor Cheng, Ron Ho, Mic...
DATE
2006
IEEE
159views Hardware» more  DATE 2006»
13 years 11 months ago
Distributed loop controller architecture for multi-threading in uni-threaded VLIW processors
Reduced energy consumption is one of the most important design goals for embedded application domains like wireless, multimedia and biomedical. Instruction memory hierarchy has be...
Praveen Raghavan, Andy Lambrechts, Murali Jayapala...
IPPS
2005
IEEE
13 years 11 months ago
Runtime Empirical Selection of Loop Schedulers on Hyperthreaded SMPs
Hyperthreaded (HT) and simultaneous multithreaded (SMT) processors are now available in commodity workstations and servers. This technology is designed to increase throughput by e...
Yun Zhang, Michael Voss
HPCA
2008
IEEE
14 years 5 months ago
PaCo: Probability-based path confidence prediction
A path confidence estimate indicates the likelihood that the processor is currently fetching correct path instructions. Accurate path confidence prediction is critical for applica...
Kshitiz Malik, Mayank Agarwal, Vikram Dhar, Matthe...