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PACS
2004
Springer
115views Hardware» more  PACS 2004»
13 years 11 months ago
Reducing Delay and Power Consumption of the Wakeup Logic Through Instruction Packing and Tag Memoization
Dynamic instruction scheduling logic is one of the most critical components of modern superscalar microprocessors, both from the delay and power dissipation standpoints. The delay ...
Joseph J. Sharkey, Dmitry Ponomarev, Kanad Ghose, ...
RTAS
1999
IEEE
13 years 10 months ago
Timing Constraint Remapping to Avoid Time Discontinuities in Distributed Real-Time Systems
In this paper we propose a dynamic constraint transformation technique for ensuring timing requirements in a distributed real-time system possessing periodically synchronized dist...
Minsoo Ryu, Jungkeun Park, Seongsoo Hong