10 search results - page 2 / 2 » C-Pack: A High-Performance Microprocessor Cache Compression ... |
FCCM
2000
IEEE
13 years 9 months ago
2000
IEEE
Although run-time reconfigurable systems have been shown to achieve very high performance, the speedups over traditional microprocessor systems are limited by the cost of configur...
DATE
2003
IEEE
13 years 10 months ago
2003
IEEE
This paper presents a new algorithm for on-the-fly data compression in high performance VLIW processors. The algorithm aggressively targets energy minimization of some of the domi...
ICCD
2008
IEEE
14 years 1 months ago
2008
IEEE
— This paper evaluates various instruction- and data-cache organizations in terms of performance, power, energy and area on a suitably selected biomedical benchmark suite. The be...
HPCA
2011
IEEE
12 years 8 months ago
2011
IEEE
Extreme technology integration in the sub-micron regime comes with a rapid rise in heat dissipation and power density for modern processors. Dynamic voltage scaling is a widely us...
FPGA
2005
ACM
13 years 10 months ago
2005
ACM
Floating-point Sparse Matrix-Vector Multiplication (SpMXV) is a key computational kernel in scientific and engineering applications. The poor data locality of sparse matrices sig...